In high speed and low noise device applications, the focus has been on designing and fabricating high electron mobility transistors (HFMTs) or modulation-doped field effect transistors (MODFETs) where carrier (eg. electrons, holes) conduction occurs in an undoped channel layer such that the carrier mobility is not limited by impurity scattering and high carrier mobility is achieved. In general, these high speed electronic devices are often used as low-noise amplifiers, power amplifiers, satellite receivers and transmitters operating in the microwave and rf regime, and the material of choice is usually the faster but more expensive III-V (e.g. GaAs) materials system and technology. A complicated and costly III-V materials technology is not very desirable in the semiconductor industry whereas a less-expensive SiGe materials system which is fully compatible with present Si technology is more desirable and far easier to integrate with existing Si-CMOS device technology.
One example of a material system compatible with Si technology is described in U.S. Pat. No. 5,019,882 which issued on May 28, 1991 to P. M. Solomon entitled “Germanium Channel Silicon MOSFET” and assigned to the assignee herein. In U.S. Pat. No. 5,019,882, a channel having improved carrier mobility comprises an alloy layer of silicon and germanium which is grown above a silicon substrate. The alloy layer is kept thin enough for proper pseudomorphic dislocation free growth. A layer of silicon is formed over the alloy layer and is oxidized partially through to form a dielectric layer. A gate region is formed over the silicon dioxide.
A second example of a high performance SiGe device structure compatible with Si technology, is described in U.S. Pat. No. 5,534,713 which issued on Jul. 9, 1996 to K. E. Ismail entitled “Complementary Metal-Oxide Semiconductor Transistor Logic Using Strained Si/SiGe Heterostructure Layers” and assigned to the assignee herein. In U.S. Pat. No. 5,534,713 a silicon CMOS transistor structure is described utilizing a buried SiGe channel under compressive strain with enhanced hole mobility for a p-channel device, and a buried Si channel under tensile strain with enhanced electron mobility for an n-channel device fabricated on a strained Si/SiGe heterostructure design. Further in U.S. Pat. No. 5,534,713 the proposed compressively-strained SiGe layer serving as a p-channel for the p-channel field effect transistor is described as having a composition of germanium in the range from 50 to 100% and with a preferred composition of 80%. Thus far, prototype SiGe p-channel MODFETs utilizing this channel design and composition at the IBM Corporation have yielded hole mobilities only up to 1,000 cm2/Vs at room temperature. Consequently, in order to achieve an even higher hole mobility of greater than 1,000 cm2/Vs, a p-channel design with a composite or dual layer structure composed of a Ge layer (of 15-20 Å thick) together with a SiGe layer of 70-80% Ge (of 70-100 Å thick) is presented as the optimum p-channel structure to produce a higher hole mobility in a SiGe materials system.